Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 4/01/2024
Document Table of Contents

1.2. CvP System

A CvP system typically consists of an FPGA, a PCIe* host, and a configuration device.

Figure 1. CvP Block Diagram for Agilex™ 7 FPGA
  1. The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme.
  2. For devices that support only one PCIe* Hard IP block on the left, the lower left PCIe* Hard IP block is used for CvP application.
  3. For devices that support two or more PCIe* Hard IP block on the left, CvP application can use either top or bottom of the PCIe* Hard IP blocks on the left side.
  4. PCIe* Hard IP blocks that are not used for CvP can be used for PCIe* application.
Note: For PCIe* design including Configuration via Protocol (CvP), Intel® recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe* wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Intel recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enter link training state before PERST# deasserted.