Visible to Intel only — GUID: nip1576107033376
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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Intel® Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
Visible to Intel only — GUID: nip1576107033376
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5.3. VSEC Registers for CvP
The Vendor Specific Extended Capability (VSEC) registers occupy byte offsets 0xD00 to 0xD4C in the PCIe* Configuration Space. The PCIe* host uses these registers to communicate with the FPGA control block. The following table shows the VSEC register map. Subsequent tables provide the fields and descriptions of each register.
Byte Offset | Register Name |
---|---|
0xD00 | Vendor Specific Capability Header |
0xD04 | Vendor Specific Header |
0xD08 | Intel Marker |
0xD0C:0xD18 | Reserved |
0xD1C | User Configurable Device/Board ID |
0xD1E | CvP Status |
0xD20 | CvP Mode Control |
0xD24 | CvP Data 22 |
0xD28 | CvP Data |
0xD2C | CvP Programming Control |
0xD30:0xD44 | Reserved |
0xD48 |
CvP Credit Register |
Section Content
Vendor Specific Capability Header Register
Vendor Specific Header Register
Intel Marker Register
User Configurable Device/Board ID Register
CvP Status Register
CvP Mode Control Register
CvP Data Registers
CvP Programming Control Register
CvP Credit Register
2 This register is no longer functional in Agilex™ 7 devices.