Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs 7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Supported PCIe* Tile 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe* Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

4.1.2.1. For CvP Initialization Mode

To meet the 120 ms wake-up time requirement for the PCIe* Hard IP in CvP initialization mode, you need to use periphery image because the configuration time for periphery image is significantly less than the full FPGA configuration time. You must use the Active Serial x4 (fast mode) configuration scheme for the periphery image configuration.

To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable1. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP Initialization mode, the PCIe* link supports the FPGA core image configuration and subsequent PCIe* applications in user mode.

Note: For PCIe* 3.0/ PCIe* 4.0 capable Endpoints, after loading the core bitstream (core.rbf), Intel recommends to verify that the link has been trained to the expected PCIe* 3.0/ PCIe* 4.0 rate. If the link is not operating at PCIe* 3.0/ PCIe* 4.0, software can trigger the Endpoint to retrain.
Figure 6.  PCIe* Timing Sequence in CvP Initialization Mode
Table 3.  Power-Up Sequence Timing in CvP Initialization Mode
Timing Sequence Timing Range (ms) Description
a

1.5–7.6

 FPGA POR delay + bootup sequence until nstatus high (AS Fast Mode).
b 80–100
Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (transceiver calibration start after reference clock is stable).
Note: During configuration, transceiver starts to perform calibration once out of reset and becomes active for link training. From power good to PCIe* link active, it has no dependency on the completion of periphery image configuration. The PCIe* Hard IP would enter link active state to meet 120ms before CONF_DONE asserted high.
c 0–20 Minimum calibration time after PERST# is deasserted.
d 100 Minimum PERST# signal active from the host.
e 120

120 ms of power stable to PCIe* link active time upon power up.

f 100 Maximum time PCIe* device must enter L0 after PERST# is deasserted.
Note: 100 ms timing range is only applicable to PCIe* PCIe* 1.0/ PCIe* 2.0. PCIe* 3.0 does not need to meet 100 ms timing requirement.
g 10 Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range
h 70–90 Periphery image loading time from nSTATUS to CONF_DONE.
Note: Agilex™ 7 F-Tile devices requires more than 120 ms to complete periphery image configuration.
Note:

The periphery configuration time may vary depending on your configuration system setup and settings.

The following conditions were used to validate the power up sequence timing in CvP initialization mode:
  • Set the VID mode of operation to PMBus Master mode
  • Use Intersil* ISL68137 regulator to regulate the PMBus
  • Set configuration clock source to OSC_CLK_1 with 125 MHz
  • No advanced security features were enabled
  • For AS x4 configuration mode, set the AS_CLK to 166 MHz. Use a Micron* device with a 2 Gb density range QSPI flash memory.
1 REFCLK must be stable 80 ms after the power supplies are stable in order to achieve the 145 ms link training complete time
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