Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

Download PDF
ID 683763
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs 7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Supported PCIe* Tile 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe* Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

1.3.1. CvP Limitations

The Agilex™ 7 device CvP implementation has the following limitations and restrictions in the current version of the Quartus® Prime software:
  • Any MemWR transaction is treated as CvP data before the device enters user mode. ConfigWR transactions are also supported.
  • When you poll the CVP_CREDIT bits from the CvP credit register, you must write the next 4 KB of fabric configuration data to the CvP data register within 50 ms of receiving an additional credit. Failure to send the data results in configuration failure.
  • The CvP response time is variable and depends on different conditions. The typical delay time is 5 sec and it is safe to wait till 1 min. So the driver should poll status in credit register to decide on driver timeout.
  • In CvP initialization and update mode, when FPGA fabric is not programmed, the PCIe* features that uses FPGA fabric are not accessible.
  • To generate the update image in the CvP update mode, you must use the same version of the Quartus® Prime software that you use to generate the base image.
  • If you use a .sof file to configure the FPGA with JTAG interface, the version of the Quartus® Prime that you used to generate the update bitstream must be the same as the version of the Quartus® Prime Programmer to program the FPGA.
  • For Agilex™ 7 designs that include the Hard Processor System (HPS), it is important to note that performing an FPGA core image update also causes the HPS to be reconfigured. The updated bitstream contains both the FPGA core data as well as the First Stage Bootloader (FSBL) used by the HPS.

Section Content
CvP Error Recovery

Level Two Title