Intel Agilex® 7 Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 8/17/2023
Document Table of Contents

6.2.1. Instantiating the PCIe Hard IP

Instantiate PCIe* Hard IP and generate the synthesis HDL files with CvP enabled. Follow the same steps from Generating the Synthesis HDL files for Intel FPGA P-Tile Avalon Streaming Interface for PCIe Express.

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