JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Document Table of Contents

1.1.3. Simulating the Design

These general steps describe how to run the design example simulation. For specific commands for each design example variant, refer to its respective section.

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory>/ed_sim/testbench/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command
    Riviera-PRO* do run_tb_top.tcl
    ModelSim* do run_tb_top.tcl
    VCS* / VCS* MX sh
    Xcelium* Parallel sh
    The simulation ends with messages that indicate whether the run was successful or not. Refer to Simulation Message and Description table in Testbench for more information on messages reported by the simulation flow.