JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Document Table of Contents

1.1.2. Generating the Design

Figure 3. Example Design Tab

To generate the design example from the IP parameter editor:

  1. Create a project targeting your device family and select the desired device.
  2. In the IP Catalog, locate and double-click Interface Protocols > JESD > JESD204B Intel® FPGA IP . The IP parameter editor appears.
  3. Specify a top-level name and the folder for your custom IP variation.. Click OK.
  4. Select a design from the Presets library by double-clicking the desired preset. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly.
  5. You can customize the preset parameter values according to your specifications. Under the IP tab, specify the JESD204B IP core parameters for your design.
    Note: The JESD204B IP core supports a limited range of parameter combinations. Refer to the Supported Configurations section for more details. If you specify an unsupported combination of parameters, the Available Example Designs automatically selects None as the default.
  6. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
    Note: To generate the design example for hardware testing on selected Intel development kits, select the appropriate target development kit from the Target Development Kit drop down box.
  7. Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.