JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Document Table of Contents

1.2.1. Features

This design example has the following key features:

  • System Console using Tcl script control mechanism
  • Synthesis and simulation flows
  • Configurable transport layer and pattern generator and checker modules
  • Power-on self test with the following configurable test patterns:
    • Alternating
    • Ramp
    • PRBS
  • Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
  • Supports option for 3-wire SPI