JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Document Table of Contents
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1.2.6. Simulation

Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.

Table 16.  Supported Simulators
Simulators Simulation Directory Run Script
Riviera-PRO* /testbench/aldec/ run_tb_top.tcl
ModelSim* /testbench/mentor/ run_tb_top.tcl
VCS* /testbench/synopsys/vcs/
VCS* MX /testbench/synopsys/vcsmx/
Xcelium* /testbench/xcelium/

The design generates the simulation results which include the transcript or log files in the relevant simulation directory.