ID 683758
Date 10/14/2022
Public

## 1.2.10.2. Changing the Data Rate or Reference Clock Frequency

When changing the data rate or reference clock frequency, you must consider the following:

• The relationships between the serial data rate, link clock, and frame clock as described in the JESD204B Intel® FPGA IP User Guide.
• Change the PLL output clock settings according to unresolvable-reference.html#sss1463109956061__table_jyd_h2w_fbb.
• Take note when changing the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters in the top level RTL file altera_jesd204_ed_<data path>.sv for cases when F=1 or F=2. These parameters further divide-down the frame clock frequency requirement so the resulting clock frequency is within bounds of timing closure for the FPGA core fabric.

The frame clock and the link clock for the following cases share the same frequency:

• F=1—the default parameter value for F1_FRAMECLK_DIV=4
• F=2—the default parameter value for F2_FRAMECLK_DIV=2
• F=4

Perform the following instructions to modify the JESD204B IP core parameters post-generation:

1. Open the generated design example project in the Intel® Quartus® Prime software.
2. Open the top level altjesd_ed_qsys_<data path>.qsys in the Platform Designer.
3. In the System Contents tab, right-click the altjesd_ss_<data path> module and select Drill into Subsystem. This opens the altjesd_ss_<data path>.qsys Platform Designer subsystem.
4. Double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
5. Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system requirements.
6. Modify the clock frequency values of the refclk_xcvr , link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules above.
7. Navigate back to the top level altjesd_ed_qsys_<data path>.qsys hierarchy.
8. For Intel® Stratix® 10 L-tile and H-tile devices, double-click the xcvr_atx_pll_0 module to bring up the parameters editor for the ATX PLL module. For Intel® Stratix® 10 E-tile devices, skip to 10.
This is the module that generates the serial clock for the TX transceiver PHY.
9. Under the PLL subtab, locate the Output Frequency group and change the PLL output frequency and PLL integer reference clock frequency values to meet your system requirements.
The PLL output frequency is half of the PLL output data rate. Ensure that the data rate and PLL reference clock values match the parameters that you entered into the JESD204B IP core module.
10. Double-click the core_pll module to bring up the parameters editor for the core PLL module.
This is the module that generates the link_clk and frame_clk clocks that clock the core components.
11. Under the PLL subtab, change the Reference Clock Frequency value in the General group to meet your system requirements.
Ensure that the reference clock frequency value matches the ones set for the JESD204B IP core and ATX PLL ( Intel® Stratix® 10 L-tile and H-tile devices) modules.
12. Change the outclk0 group settings (which correspond to the link_clk) and outclk1 group settings (which correspond to the frame_clk) where necessary.
Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in the JESD204B IP Core User Guide.
13. Modify the clock frequency values of the refclk_xcvr , refclk_core, link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules in earlier steps.
14. Click the Generate HDL button to generate the HDL files needed for Intel® Quartus® Prime compilation.
15. After the HDL generation is completed, click the Finish to save your Platform Designer settings and exit the Platform Designer window.
16. If the frame_clk settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values are changed, change the parameters in the top level design file, altera_jesd204_ed_<data path>.sv.
17. Modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect your new clock frequency values, if applicable. The following constraints should be modified:
create_clock -name refclk_xcvr -period <clock period value in ns> [get_nodes refclk_xcvr]
create_clock -name mgmt_clk -period <clock period value in ns> [get_nodes mgmt_clk]
18. Save the file and compile the design in Intel® Quartus® Prime software as per the instructions in the Compiling and Testing the Design.

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