JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1.4.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the JESD204B IP core is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 4.   Intel® Stratix® 10 GX FPGA Development Kit Board Connectivity for H-Tile DevicesThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for Intel® Stratix® 10 GX FPGA development kit.
Port Name Port Description Board Component Component Description
global_rst_n Global reset S5 User PB0 push-button
refclk_xcvr Transceiver reference clock input U7 Si5341 clock generator (OUT4)
refclk_core Core PLL reference clock input U7 Si5341 clock generator (OUT7)
mgmt_clk Control clock U9 Si5338 clock generator (CLK1)
tx_serial_data TX serial data J13 FMC port A connector
rx_serial_data RX serial data J13 FMC port A connector
Table 5.   Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit Board Connectivity for E-Tile DevicesThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for Intel® Stratix® 10 TX Transceiver Signal Integrity development kit.
Port Name Port Description Board Component Component Description
global_rst_n Global reset S8 S8 push-button
refclk_xcvr Transceiver reference clock input Engineering sample version board revision A (non-bonded channels) and production version board revision B (non-bonded channels)
U3 Si5341 clock generator (OUT8)
Production version board revision B (bonded channels)
U3 Si5341 clock generator (OUT4)
refclk_core Core PLL reference clock input U3 Si5341 clock generator (OUT2)
mgmt_clk Control clock U3 Si5341 clock generator (OUT3)
tx_serial_data TX serial data Engineering sample version board revision A (non-bonded, up to 4 channels)
U32-1

Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector)

Engineering sample version board revision A (non-bonded, 5–8 channels)
U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector)

Production version board revision B (non-bonded, up to 8 channels)
J27D

Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)

Production version board revision B (bonded, up to 4 channels)
U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)

Production version board revision B (bonded, 5–8 channels)
U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector

rx_serial_data RX serial data Engineering sample version board revision A (non-bonded, up to 4 channels)
U32-1

Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector)

Engineering sample version board revision A (non-bonded, 5–8 channels)
U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector)

Production version board revision B (non-bonded, up to 8 channels)
J27D

Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)

Production version board revision B (bonded, up to 4 channels)
U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)

Production version board revision B (bonded, 5–8 channels)
U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)

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