JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2.7. Design Example Files

There are two flows for the design example: simulation and synthesis.

Table 18.  Design Example Flows and Directory
Design Example Flow Directory
Simulation <your project>/ed_sim
Synthesis <your project>/ed_synth

The following tables list the important folders and files for simulation and synthesis.

Table 19.  Design Example Files for Simulation
File Type File/Folder Description
Run script files /testbench/aldec/run_tb_top.tcl TCL run script for Riviera-PRO* simulator
/testbench/mentor/run_tb_top.tcl TCL run script for ModelSim* or QuestaSim* simulator
/testbench/synopsys/vcs/run_tb_top.sh Shell run script for VCS* simulator
/testbench/synopsys/vcsmx/run_tb_top.sh Shell run script for VCS* MX simulator
/testbench/xcelium/run_tb_top.sh Shell run script for Xcelium* simulator
Source files /testbench/models/altjesd_ed_qsys_<data path>.qsys Top level Platform Designer system project
/testbench/models/altjesd_ss_<data path>.qsys JESD204B subsystem Platform Designer system project
/testbench/models/ip/ IP folder containing instantiated IP modules
/testbench/models/altera_jesd204_ed_<data path>.sv Top level HDL
/testbench/models/tb_top.sv Top level testbench
/testbench/spi_mosi_oe.v Output buffer HDL
/testbench/switch_debouncer.v Switch debouncer HDL
/testbench/pattern/ Folder containing the test pattern generator and checker HDL
/testbench/transport_layer Folder containing assembler and de-assembler HDL.
Table 20.  Design Example Files for Synthesis
File Type File/Folder Description
Intel® Quartus® Prime project files altera_jesd204_ed_<data path>.qpf Intel® Quartus® Prime project file
altera_jesd204_ed_<data path>.qsf Intel® Quartus® Prime settings file
Source files altera_jesd204_ed_<data path>.sv Top level HDL
altera_jesd204_ed_<data path>.sdc Synopsys* Design Constraints (SDC) file containing all timing/placement constraints
transport_layer/ Folder containing assembler and de-assembler HDL
pattern/ Folder containing the test pattern generator and checker HDL
spi_mosi_oe.v Output buffer HDL
switch_debouncer.v Switch debouncer HDL
altjesd_ed_qsys_<data path>.qsys Top level Platform Designer system project
altjesd_ss_<data path>.qsys JESD204B subsystem Platform Designer system project
Level Two Title