JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Document Table of Contents Design Example Parameters

The JESD204B IP parameter editor includes a Example Design tab for you to specify certain parameters before generating the design example.
Table 2.  Parameters in the Example Design Tab
Parameter Options Description
Available Example Designs None (Default) No design examples selected.
System Console Control Design example with System Console control.
Example Design Files Simulation Generate simulation fileset.
Synthesis Generate synthesis fileset.
Generated HDL Format for Simulation Verilog (Default) Verilog HDL format for entire simulation fileset.
VHDL VHDL format for generated top-level wrapper file set.
Generated HDL Format for Synthesis Verilog (Default) Verilog HDL format for synthesis fileset.
Example Design Customizations Generate 3-wire SPI module Check to enable 3-wire SPI interface instead of 4-wire SPI interface.