JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2.5.5. Clocking Scheme

The main reference clocks for the design example are refclk_core and refclk_xcvr. These clocks must be supplied from a single external source (i.e refclk_core and refclk_xcvr must be synchronous to one another). The refclk_core is the reference clock for the core PLL and the refclk_xcvr is the reference clock for the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from refclk_core.

The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon memory-mapped interfaces of Platform Designer components.

Table 15.  System Clocking for the Design Example
Clock Description Source Modules Clocked
refclk_core Reference clock for the core PLL External Core PLL
refclk_xcvr Reference clock for the ATX PLL ( Intel® Stratix® 10 L-tile and H-tile devices), TX PLL ( Intel® Stratix® 10 E-tile devices), and RX transceiver PHY External ATX PLL ( Intel® Stratix® 10 L-tile and H-tile devices), TX PLL ( Intel® Stratix® 10 E-tile devices), and RX transceiver PHY
link_clk Link layer clock refclk_core JESD204B IP core link layer, transport layer link interface
frame_clk Frame layer clock refclk_core Transport layer, test pattern generator and checker, downstream modules
mgmt_clk Control plane clock External Avalon memory-mapped interfaces
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