1.2.5. Functional Description
The design example consists of various components.
The following block diagram shows the design components and the top-level signals of the design example.
Figure 9. JESD204B Design Example Block Diagram
- Platform Designer system
- JESD204B subsystem
- JTAG to Avalon master bridge—For System Console Control design example only
- Parallel I/O (PIO)
- ATX PLL (Applicable only for Intel® Stratix® 10 L-tile and H-tile devices)
- Core PLL
- Serial Port Interface (SPI)—master module
- Test pattern generator (For duplex and simplex TX data path only)
- Test pattern checker (For duplex and simplex RX data path only)
- Assembler—TX transport layer (For duplex and simplex TX data path only)
- Deassembler—RX transport layer (For duplex and simplex RX data path only)
Did you find the information on this page useful?