1.1. Boot Process 1.2. Boot Stages 1.3. Boot Devices 1.4. Second-Stage Boot Loader Support Package Generator Tool 1.5. Generating a Boot Loader with an External Flash Boot Device 1.6. Boot and FPGA Configuration 1.7. Boot Debugging 1.8. Appendix A: Building the UEFI Boot Loader 1.9. Revision History for Arria 10 SoC Boot User Guide
1.8.6. UEFI Generated Files
Compiling the UEFI source code creates the following files in the /data/<username>/pggit/uefi-socfpga/Build/ folder:
|~ /uefi-socfpga/Build/PEI.256 (256KB)||
This file is generated from the mkpimage tool by adding a header to the original file located at ~/uefisocfpga/ Build/Arria10SoCPkg/RELEASE_GCC48/FV/ALTERA_HPS_OCRAM_EFI_ PART1.fd. The file loads directly into the on-chip RAM using DS-5 because it is only 256 KB in size.
This file generates the PEI.ROM file.
|~ /uefi-socfpga/Build/PEI.ROM (1MB = 256KB X 4)||This file is programmed onto the flash daughter card. The size of this file is four times bigger because the the boot ROM can support up to four backup images. For example, if the first image (256KB) is corrupted, the boot ROM loads the second image and so on.|
|~ /uefi-socfpga/Build/load_uefi_fw.ds||This is the DS-5 script template. It is imported to the DS-5 tool and loads the UEFI firmware for debug and development purposes. This script loads the debug symbols for the user. Currently, it only supports the GCC compiler. ARMCC is not supported.|
|~ /uefi-socfpga/Build/DXE.ROM||This file is currently not in use. Reserved for future use.|
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