Arria® 10 SoC Boot User Guide

ID 683735
Date 4/03/2019
Document Table of Contents

1.2.1. Reset

Reset precedes the boot stages and is an important part of device initialization. There are two different reset types: cold reset and warm reset.

The FPGA portion of the SoC can trigger a warm or cold reset on completion of configuration.

The boot process begins when CPU0 in the MPU exits from the reset state. When CPU0 exits from reset, it starts executing code at the reset exception address where the boot ROM code is located. CPU1 remains in reset during this time and is brought out of reset by user software.

With warm reset, some software registers are preserved and the boot process may skip some steps depending on software settings. In addition, on a warm reset, the second-stage boot loader has the ability to be executed from on-chip RAM.

Note: It is important that the HPS is not held in cold or warm reset indefinitely, otherwise the CSS will not be accessible to FPGA configuration sources.