Arria® 10 SoC Boot User Guide

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ID 683735
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Arria 10 SoC Boot User Guide
1. Arria 10 SoC Boot User Guide x
1.1. Boot Process 1.2. Boot Stages 1.3. Boot Devices 1.4. Second-Stage Boot Loader Support Package Generator Tool 1.5. Generating a Boot Loader with an External Flash Boot Device 1.6. Boot and FPGA Configuration 1.7. Boot Debugging 1.8. Appendix A: Building the UEFI Boot Loader 1.9. Revision History for Arria 10 SoC Boot User Guide
1.1. Boot Process x
1.1.1. Typical Boot Flow 1.1.2. Bare Metal Boot Flow 1.1.3. Custom Boot Loader
1.2. Boot Stages x
1.2.1. Reset 1.2.2. First Stage: Boot ROM 1.2.3. Second Stage: Boot Loader (U-Boot)
1.2.2. First Stage: Boot ROM x
1.2.2.1. Boot ROM Flow
1.2.3. Second Stage: Boot Loader (U-Boot) x
1.2.3.1. Second-Stage Boot Flow
1.2.3.1. Second-Stage Boot Flow x
1.2.3.1.1. Typical Boot Flow (Non-Secure) 1.2.3.1.2. Secure Boot Flow
1.3. Boot Devices x
1.3.1. Boot Select 1.3.2. Flash Memory Devices for Booting 1.3.3. Booting From FPGA
1.3.2. Flash Memory Devices for Booting x
1.3.2.1. Quad SPI Flash Devices 1.3.2.2. SD/MMC Flash Devices 1.3.2.3. NAND Flash Devices
1.4. Second-Stage Boot Loader Support Package Generator Tool x
1.4.1. Boot Loader Generation and Flow
1.4.1. Boot Loader Generation and Flow x
1.4.1.1. Step 1: Compiling the FPGA Design 1.4.1.2. Step 2: Hardware Hand-off Files 1.4.1.3. Step 3: Generating the Boot Loader Source 1.4.1.4. Boot Loader Generator Tool: BSP Editor
1.5. Generating a Boot Loader with an External Flash Boot Device x
1.5.1. Prerequisites 1.5.2. Boot Loader Generation Example Using an SD/MMC Controller 1.5.3. Boot Loader Generation Example Using a QSPI Flash Controller 1.5.4. Boot Loader Generation Example Using a NAND Flash Controller
1.7. Boot Debugging x
1.7.1. Cold Boot Debug 1.7.2. Warm Boot Debug 1.7.3. Using the Boot ROM and Boot Loader Debug Registers 1.7.4. Boot Flash Device Issues 1.7.5. HPS Boot Loader Debugging
1.8. Appendix A: Building the UEFI Boot Loader x
1.8.1. Prerequisites 1.8.2. Supported Compiler Toolchains 1.8.3. Obtaining the UEFI Source Code 1.8.4. Compiling the UEFI Source Code with the Linaro Tool Chain 1.8.5. Compiling the UEFI Source Code with the ARM Tool Chain 1.8.6. UEFI Generated Files
1. Arria 10 SoC Boot User Guide

1.3.1. Boot Select

The boot select (BSEL) pins offer multiple methods to obtain the second-stage boot image. On a cold reset, the boot source is determined by a combination of secure boot fuses and BSEL pins. These fuse values and BSEL pin values are sent to the Security Manager module of the HPS when the cold reset occurs. When the HPS is released from reset, the boot ROM reads the bootinfo register of the System Manager to determine the source of the boot.

Note: If the fpga_boot_f fuse is blown, the BSEL pins are bypassed and the HPS can only boot from the FPGA. Additionally, the clock select (CSEL) fuse values are ignored and clock configuration is controlled through the FPGA. This configuration allows the HPS to boot from encrypted user code in the FPGA. If the boot source is the FPGA, the boot ROM code does not configure any of the boot-specific HPS I/Os for booting from flash memory. If the fpga_boot_f fuse is not blown, then the boot source is determined according to the BSEL pins. If the BSEL pins are used for determining the boot source, then the following table shows the flash devices assigned to each encoding.
Note: When booting from FPGA is selected (BSEL[2:0]=0x1), the Boot ROM waits until the FPGA is in user mode, and then it queries the handshake signals, f2h_boot_from_fpga_ready and f2h_boot_from_fpga_on_failure, from the FPGA to the HPS. The f2h_boot_from_fpga_ready signal must be pulled up to indicate readiness. Refer to the Instantiating the HPS Component chapter for more information about the FPGA boot handshake signals.
Note: The acronyms BSEL and BOOTSEL are used interchangeably to define the boot select pins.
Table 1.  BSEL Values for Boot Source Selection
BSEL[2:0] Value Flash Device
0x0 Reserved
0x1 FPGA (HPS-to-FPGA bridge)
0x2 1.8 V NAND flash memory
0x3 3.0 V NAND flash memory
0x4 1.8 V SD/MMC flash memory with external transceiver
0x5 3.0 V SD/MMC flash memory with internal transceiver
0x6 1.8 V quad SPI flash memory
0x7 3.0 V quad SPI flash memory
Note: During the HPS boot phase, the boot ROM only recognizes 1.8 V or 3.0 V dedicated I/O operation. If your dedicated I/O are operating at 2.5 V, then your BSEL value must be set to 3.0 V to support your operating I/O voltage at boot. After booting has completed, you may configure your dedicated I/O voltage settings to the true level by programming the configuration_dedicated_io_bank and configuration_dedicated_io_* registers in the io48_pin_mux_dedicated_io_grp address block.
Note: If the BSEL value is set to 0x4 or 0x5, an external translation transceiver may be required to supply level-shifting and isolation if the SD cards interfacing to the SD/MMC controller must operate at a different voltage than the controller interface. Please refer to the SD/MMC Controller chapter for more information.

The typical boot flow is for the boot ROM code to find the second-stage boot loader image on a flash device, load that into on-chip RAM and execute it. After a warm reset, the boot ROM code can be instructed to find the image in RAM and execute that.

The HPS flash sources can store various file types, such as:

  • FPGA programming files
  • Second-stage boot loader binary file (up to four copies)
  • Operating system binary files
  • Application file system

The second-stage boot loader image in flash can be authenticated and decrypted by the HPS. A boot directly from the HPS on-chip RAM is always unauthenticated and in clear text, although it may have an optional CRC if required.

When the BSEL value is 0x1, the FPGA is selected as the boot source for that boot. This selection is not permanent as it is when the fpga_boot_f fuse is enabled. In both cases, the CSEL fuses are also ignored and the HPS must be held in reset until the FPGA is powered on and programmed to prevent the boot ROM from misinterpreting the boot source.

If an HPS flash interface has been selected to load the boot image, then the boot ROM enables and configures that interface before loading the boot image into on-chip RAM, verifying it and passing software control to the second-stage boot loader.

If the FPGA fabric is the boot source, the boot ROM code waits until the FPGA portion of the device is in user mode, and is ready to execute code and then passes software control to the second-stage boot loader in the FPGA RAM.

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