Arria® 10 SoC Boot User Guide

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ID 683735
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Arria 10 SoC Boot User Guide
1. Arria 10 SoC Boot User Guide x
1.1. Boot Process 1.2. Boot Stages 1.3. Boot Devices 1.4. Second-Stage Boot Loader Support Package Generator Tool 1.5. Generating a Boot Loader with an External Flash Boot Device 1.6. Boot and FPGA Configuration 1.7. Boot Debugging 1.8. Appendix A: Building the UEFI Boot Loader 1.9. Revision History for Arria 10 SoC Boot User Guide
1.1. Boot Process x
1.1.1. Typical Boot Flow 1.1.2. Bare Metal Boot Flow 1.1.3. Custom Boot Loader
1.2. Boot Stages x
1.2.1. Reset 1.2.2. First Stage: Boot ROM 1.2.3. Second Stage: Boot Loader (U-Boot)
1.2.2. First Stage: Boot ROM x
1.2.2.1. Boot ROM Flow
1.2.3. Second Stage: Boot Loader (U-Boot) x
1.2.3.1. Second-Stage Boot Flow
1.2.3.1. Second-Stage Boot Flow x
1.2.3.1.1. Typical Boot Flow (Non-Secure) 1.2.3.1.2. Secure Boot Flow
1.3. Boot Devices x
1.3.1. Boot Select 1.3.2. Flash Memory Devices for Booting 1.3.3. Booting From FPGA
1.3.2. Flash Memory Devices for Booting x
1.3.2.1. Quad SPI Flash Devices 1.3.2.2. SD/MMC Flash Devices 1.3.2.3. NAND Flash Devices
1.4. Second-Stage Boot Loader Support Package Generator Tool x
1.4.1. Boot Loader Generation and Flow
1.4.1. Boot Loader Generation and Flow x
1.4.1.1. Step 1: Compiling the FPGA Design 1.4.1.2. Step 2: Hardware Hand-off Files 1.4.1.3. Step 3: Generating the Boot Loader Source 1.4.1.4. Boot Loader Generator Tool: BSP Editor
1.5. Generating a Boot Loader with an External Flash Boot Device x
1.5.1. Prerequisites 1.5.2. Boot Loader Generation Example Using an SD/MMC Controller 1.5.3. Boot Loader Generation Example Using a QSPI Flash Controller 1.5.4. Boot Loader Generation Example Using a NAND Flash Controller
1.7. Boot Debugging x
1.7.1. Cold Boot Debug 1.7.2. Warm Boot Debug 1.7.3. Using the Boot ROM and Boot Loader Debug Registers 1.7.4. Boot Flash Device Issues 1.7.5. HPS Boot Loader Debugging
1.8. Appendix A: Building the UEFI Boot Loader x
1.8.1. Prerequisites 1.8.2. Supported Compiler Toolchains 1.8.3. Obtaining the UEFI Source Code 1.8.4. Compiling the UEFI Source Code with the Linaro Tool Chain 1.8.5. Compiling the UEFI Source Code with the ARM Tool Chain 1.8.6. UEFI Generated Files
1. Arria 10 SoC Boot User Guide

1.5.4. Boot Loader Generation Example Using a NAND Flash Controller

  1. Launch the SoC EDS embedded command shell: 
    $ ~/intelFPGA/16.1/embedded/embedded_command_shell.sh
  2. Launch the BSP Editor tool from the SoC EDS embedded command shell: 
    $ bsp-editor
  3. Create a new HPS BSP in the window by selecting File > New HPS BPS.
    Figure 29. Selecting New BSP Editor Window
  4. In the New BSP pop-up window, configure the following:
    1. Specify a hardware HPS hand-off folder in the Preloader settings directory.
    2. Specify the boot loader sources folder in the BSP target directory text box.
    3. Specify the boot loader configuration and settings file location in the BSP Settings File name text box.
    Figure 30. Configuring New BSP Settings
  5. Click OK to close the New BSP pop-up window.
  6. In the BSP Editor window, specify the source boot_device (NAND) in the main menu tab.
    Figure 31. Selecting Boot from NAND Device in BSP Editor Window
  7. Select Generate and the boot loader and U-Boot source files are created in the folder you specified as the BSP target directory.
  8. Change to the U-Boot boot loader source directory and build the image: 
    $ cd ~/a10_soc_devkit_ghrd/software/arria10_uboot_bsp
$ make

    The following items are generated in the ~/a10_soc_devkit_ghrd/software/arria10_uboot_bsp/ folder:

    Table 7.  Boot Loader Executable Images
    File Description
    u-boot_w_dtb.bin U-boot executable with device tree binary
    uboot_w_dtb-mkpimage.bin U-boot executable with device tree binary wrapped in mkpimage header
    Note: If you choose to use UEFI as a second-stage boot loader source, refer to the "Appendix A: Building the UEFI Boot Loader" section at this point.
  9. Prepare the boot loader image, U-Boot device tree and FPGA design on the boot device. For more information, please refer to the RocketBoards.org website.
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