1.1.1. Typical Boot Flow
The booting of the HPS is a multi-stage process. Each stage is responsible for loading the next stage.
The first stage is the boot ROM execution. The boot ROM code, located in the HPS, brings the processor out of reset, puts the processor into a known and stable state, finds the second-stage boot loader and passes control to the next stage. The boot ROM code is only aware of the second-stage boot loader and not aware of any potential subsequent software stages. During this time, the boot ROM also seamlessly handles any error conditions.
The next stage is when control passes to the second-stage boot loader. The second-stage boot loader is located external to the HPS, either in external flash memory or within the FPGA. If the FPGA is used, the second stage boot loader can execute directly from the FPGA without the need to copy it to on-chip RAM. The second-stage boot loader locates and loads the next stage software and so on.
Before control is passed to the second stage boot loader, it can be decrypted and/or authenticated if secure boot is enabled.
After a warm reset, the user can instruct the boot ROM to find an image in the on-chip RAM and execute directly from that. In this case, the image that resides in RAM is unauthenticated and clear text, although it may have been imported into on-chip RAM as authenticated code initially.
The figure below illustrates the typical boot flow. However, there may be more or less software stages in the user software than shown and the roles of the software stages may vary.
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