Arria® 10 SoC Boot User Guide

ID 683735
Date 4/03/2019
Document Table of Contents

1.5.3. Boot Loader Generation Example Using a QSPI Flash Controller

  1. Launch the SoC EDS embedded command shell:
    $ ~/altera/15.0/embedded/
  2. Launch the BSP Editor tool from the SoC EDS embedded command shell:
    $ bsp-editor
  3. Create a new HPS BSP in the window by selecting File > New HPS BPS .
    Figure 26. Selecting New BSP Editor Window
  4. In the New BSP pop-up window, configure the following:
    1. Specify a hardware HPS hand-off folder in the Preloader settings directory.
    2. Specify the boot loader sources folder in the BSP target directory text box.
    3. Specify the boot loader configuration and settings file location in the BSP Settings File name text box.
    Figure 27. Configuring New BSP Settings
  5. Click OK to close the New BSP pop-up window.
  6. In the BSP Editor window,specify the source boot_device (QSPI) in the main menu tab.
    Note: The .rbf files only apply when booting from SD/MMC. For QSPI configuration, these text boxes do not need to be edited, but instead a single .rbf file must be created through a conversion script.
    Figure 28. Selecting Boot from QSPI Device in BSP Editor Window
  7. Select Generate and the boot loader and U-Boot source files are created in the folder you specified as the BSP target directory.
  8. Change to the U-Boot boot loader source folder and build the image.
    $ cd ~/a10_soc_devkit_ghrd/software/arria10_uboot_bsp
    $ make

    The following items are generated in the ~/a10_soc_devkit_ghrd/software/arria10_uboot_bsp/ folder:

    Table 6.  Boot Loader Executable Images
    File Description
    u-boot_w_dtb.bin U-boot executable with device tree binary
    uboot_w_dtb-mkpimage.bin U-boot executable with device tree binary wrapped in mkpimage header
    Note: If you choose to use UEFI as a second-stage boot loader source, refer to the "Appendix A: Building the UEFI Boot Loader" section at this point.
  9. Prepare the boot loader image, U-Boot device tree and FPGA design on the boot device. For more information, please refer to the website.