Intel® FPGA Download Cable II User Guide

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ID 683719
Date 8/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. Setting Up the Intel® FPGA Download Cable II 2. Intel® FPGA Download Cable II Specifications 3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II 4. Document Revision History for the Intel® FPGA Download Cable II User Guide A. Additional Information
1. Setting Up the Intel® FPGA Download Cable II x
1.1. Supported Devices and Systems 1.2. Power Source Requirements 1.3. Software Requirements and Support 1.4. Installing the Intel® FPGA Download Cable II for Configuration or Programming 1.5. Installing the Intel® FPGA Download Cable II Driver on Windows 7/8/10/11 Systems 1.6. Installing the Intel® FPGA Download Cable II Driver on Linux Systems 1.7. Setting Up the Intel® FPGA Download Cable II Hardware with the Quartus® Prime Software
2. Intel® FPGA Download Cable II Specifications x
2.1. Voltage Requirements 2.2. Cable-to-Board Connection 2.3. Intel® FPGA Download Cable II Plug Connection 2.4. 10-Pin Female Plug Signal Names and Programming Modes 2.5. Circuit Board Header Connection 2.6. Operating Conditions 2.7. JTAG Timing Constraints and Waveforms 2.8. Changing the TCK Frequency
3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II x
3.1. Turn ON/OFF Auto-Adjust Feature
A. Additional Information x
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable II A.2. Troubleshooting Procedure for Error when scanning hardware - No Devices A.3. Certification Statements
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable II x
A.1.1. Jtagconfig Version Setting ( Quartus® Prime software root directory setting) A.1.2. Jtagserver Setting A.1.3. Install/Reinstall the Intel® FPGA Download Cable II driver
A.1.1. Jtagconfig Version Setting ( Quartus® Prime software root directory setting) x
A.1.1.1. Automatic Setting A.1.1.2. Manual Setting
A.3. Certification Statements x
A.3.1. RoHS Compliance A.3.2. USB 2.0 Certification A.3.3. CE EMI Conformity Caution
1. Setting Up the Intel® FPGA Download Cable II
2. Intel® FPGA Download Cable II Specifications
3. TCK Frequency Auto-Adjust for Intel® FPGA Download Cable II
4. Document Revision History for the Intel® FPGA Download Cable II User Guide
A. Additional Information

2.7. JTAG Timing Constraints and Waveforms

Figure 6. Timing Waveform for JTAG Signals (From Target Device Perspective)

To use the Intel® FPGA Download Cable II at the maximum capability (24 MHz), meet the timing constraints like in the JTAG Timing Constraints for the Target Device table below for the target device.

The timing constraints require that you consider device specifications as well as trace propagation delays. If you do not follow the recommended constraints, you might encounter timing issues at 24 MHz. If the target design cannot meet these constraints, reduce the possibility of timing issues by slowing the TCK frequency. See the Changing the TCK Frequency section for instructions on running the download cable at a slower speed.

Table 7.  JTAG Timing Constraints for the Target Device
Symbol Parameter Min Max Unit
tJCP TCK clock period 41.67 — ns
tJCH TCK clock high time 20.83 — ns
tJCL TCK clock low time 20.83 — ns
tJPCO JTAG port clock to JTAG Header output — 5.46 (2.5 V)

2.66 (1.5 V)

 ns
tJPSU_TDI JTAG port setup time (TDI) — 24.42 ns
tJPSU_TMS JTAG port setup time (TMS) — 26.43 ns
tJPH JTAG port hold time — 17.25 ns

The simulated timing is based on a slow timing model, which is a worst-case scenario environment.

For device-specific JTAG timing information, refer to the related device data sheet.

Figure 7. Intel FPGA Download Cable II Timing Constraints

If you cannot meet 24 MHz, you must decrease the frequencies to 16-6 MHz. Below is some example code to set the TCK maximum frequency to 6 MHz: 

jtagconfig --setparam 1 JtagClock 6M
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