Intel® FPGA Download Cable II User Guide

ID 683719
Date 8/26/2022
Document Table of Contents

2.7. JTAG Timing Constraints and Waveforms

Figure 6. Timing Waveform for JTAG Signals (From Target Device Perspective)

To use the Intel® FPGA Download Cable II at the maximum capability (24 MHz), meet the timing constraints like in the tabe below for the target device.

The timing constraints require that you consider device specifications as well as trace propagation delays. If you do not follow the recommended constraints, you might encounter timing issues at 24 MHz. If the target design cannot meet these constraints, reduce the possibility of timing issues by slowing the TCK frequency. See “Changing the TCK Frequency” section for instructions on running the download cable at a slower speed.

Table 7.  JTAG Timing Constraints for the Target Device
Symbol Parameter Min Max Unit
tJCP TCK clock period 41.67 ns
tJCH TCK clock high time 20.83 ns
tJCL TCK clock low time 20.83 ns
tJPCO JTAG port clock to JTAG Header output 5.46 (2.5 V)

2.66 (1.5 V)

tJPSU_TDI JTAG port setup time (TDI) 24.42 ns
tJPSU_TMS JTAG port setup time (TMS) 26.43 ns
tJPH JTAG port hold time 17.25 ns

The simulated timing is based on a slow timing model, which is a worst-case scenario environment.

For device-specific JTAG timing information, refer to the related device data sheet.

Figure 7. Intel FPGA Download Cable II Timing Constraints

If you cannot meet 24 MHz, you must decrease the frequencies to 16-6 MHz. Below is some example code to set the TCK maximum frequency to 6 MHz:

jtagconfig --setparam 1 JtagClock 6M

Did you find the information on this page useful?

Characters remaining:

Feedback Message