2.4. 10-Pin Female Plug Signal Names and Programming Modes
Pin | Active Serial (AS) Mode | Passive Serial (PS) Mode | JTAG Mode | |||
---|---|---|---|---|---|---|
Signal Name | Description 1 | Signal Name | Description1 | Signal Name | Description1 | |
1 | DCLK | Configuration Clock | DCLK | Configuration Clock | TCK | Test Clock |
2 | GND | Signal ground | GND | Signal ground | GND | Signal ground |
3 | CONF_DONE | Configuration done | CONF_DONE | Configuration done | TDO | Test Data Output |
4 | VCC(TRGT) | Target power supply | VCC(TRGT) | Target power supply | VCC(TRGT) | Target power supply |
5 | nCONFIG | Configuration control | nCONFIG | Configuration control | TMS | Test Mode Select Input |
6 | nCE | Target chip enable | - | - | PROC_RST | Processor Reset |
7 | DATAOUT | Active serial data out | nSTATUS | Configuration Status | - | - |
8 | nCS | Serial configuration device chip select | nCS | Serial configuration device chip select | - | - |
9 | ASDI | Active serial data in | DATA0 | Passive serial data in | TDI | Test Data Input |
10 | GND | Signal ground | GND | Signal ground | GND | Signal ground |
Note: Use pin 6 for hard processor reset under JTAG mode.
Note: The following note below only applies to Intel® Arria® 10 and earlier SoC devices. PROC_RST is not used for Intel® Stratix® 10 SoC devices.
In JTAG mode, the PROC_RST pin can be used to trigger warm reset of the HPS block when prompted via the ARM DS-5 debugger. PROC_RST is an active low signal and not an open collector pin. As such, it is not recommended to connect PROC_RST to HPS_nRST directly. You should instead connect this pin to a secondary device such as the MAX V CPLD, and use the device to manage the reset network for HPS.
1 The input or output pin described is referring to the pin of the FPGA device. For more information, refer to the Configuration User Guide or Device Pin Connection Guidelines of the respective FPGA device.
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