## PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 9/01/2021
Public

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## 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints

The Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint ensure that the data output from the FPGA to the external device meets the setup and hold requirements of the external device. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.

The following figure shows the considerations required to determine the Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint values. These constraints are depending on the clock and data traces, and setup and hold requirements of the external device. With system-centric delays, you can obtain the setup and hold requirements, clock delay, and data trace delay values for the external device through the device data sheet.

Figure 80. Output Strobe Setup and Hold Delay Constraints Considerations

The following is the derivation for Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint:

Output strobe setup delay constraint = Maximum board skew + maximum tSU

Output strobe hold delay constraint = Minimum board skew + minimum tH

where maximum board skew = maximum data trace - minimum clock trace

minimum board skew = minimum data trace - maximum clock trace

maximum tSU = clock setup time

minimum tH = clock hold time

Figure 81. DDR Output Cycle Timing Diagram
The following is an example of Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint calculations with:
• Input clock frequency = 100 MHz
• Board skew estimation = ± 0.03 ns
• Maximum tSU = 0.75 ns
• Minimum tH = 0.75 ns

Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns

Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns

Insert these values into the Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint parameters and run timing analysis with the Timing Analyzer tool. The following is an example of delay result from the Timing Analyzer tool.
Figure 82. Example of Output Strobe Delay Value from Timing Analyzer