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- 188.8.131.52.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers
184.108.40.206. Input Path Data Alignment
The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.
The rdata_valid delay is always set by the IP to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).
Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs. This request causes the IP to do two or more read operations.
The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus.
The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid.
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