PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 9/01/2021

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Document Table of Contents Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel Interfaces IP, each with one bidirectional group composed of 4 data bits and one strobe. Both interfaces are in the same I/O column and therefore their tables must be merged.

Figure 70. Parameter Table Example for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Important: There is no guarantee of the ordering of the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the Address Lookup topic.