PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 9/01/2021
Public

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2.2.2. Intel® Agilex™ Input DQS/Strobe Tree

The input DQS/strobe tree is a balanced clock network that distributes the read capture strobe (such as DQS/DQS#) from the external device to the read capture registers inside the I/Os.

The DQS/strobe tree is used for input and bidirectional pin types.

Within every bank, only certain physical pins at specific locations can drive the input DQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary, depending on the size of the group.

Table 2.  Pins Usable as Read Capture Clock / Strobe Pair
Bank Lane used by Data Pins Group Size Strobe Pins 1 2
0 x8 / x9 Pin 4, 5
1 x8 / x9 Pin 16, 17
2 x8 / x9 Pin 28, 29
3 x8 / x9 Pin 40, 41
0, 1 x18 Pin 4, 5
2, 3 x18 Pin 28, 29
1, 2 x36 Pin 16, 17
0, 1, 2 x36 Pin 16, 17
1, 2, 3 x36 Pin 16, 17
0, 1, 2, 3 x36 Pin 16, 17
1 For strobe pin, use either pin for single-ended and use both pins for differential.
2 In quarter rate, unused strobe pin cannot be used as data pins.