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- 184.108.40.206.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers
220.127.116.11.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
The Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters ensure that an input to the FPGA from the an external device meets the internal FPGA setup and hold time requirements. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values. The external device sends data and clock to the FPGA through interconnect on the board. The FPGA uses the clock signal from the external device to latch input data to the FPGA. The maximum and minimum values of the output clock TCO are values available in the external device data sheet.
The following is the derivation for Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint:
Input strobe setup delay constraint = Maximum board skew + maximum TCO
Input strobe hold delay constraint = Minimum board skew + minimum TCO
where maximum board skew = maximum data trace - minimum clock trace
minimum board skew = minimum data trace - maximum clock trace
maximum TCO = DQS to DQ skew (tDQSQ)
minimum TCO = Data hold skew (tQHS)
- Input clock frequency = 100 MHz
- Board skew estimation = ± 0.03 ns
- Maximum TCO = 0.6 ns
- Minimum TCO = -0.6 ns
Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns
Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns
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