A newer version of this document is available. Customers should click here to go to the newest version.
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP 3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
188.8.131.52.1. Timing Closure: Dynamic Reconfiguration 184.108.40.206.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 220.127.116.11.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 18.104.22.168.4. Timing Closure: Non Edge-Aligned Input Data 22.214.171.124.5. I/O Timing Violation 126.96.36.199.6. Internal FPGA Path Timing Violation
188.8.131.52.1. Timing Closure: Dynamic Reconfiguration 184.108.40.206.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 220.127.116.11.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 18.104.22.168.4. Timing Closure: Non Edge-Aligned Input Data 22.214.171.124.5. I/O Timing Violation 126.96.36.199.6. Internal FPGA Path Timing Violation
- 188.8.131.52.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers
184.108.40.206. RZQ_GROUP Assignment
The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT Intel FPGA IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP instance with an RZQ pin at the system level manually.
Use the following steps to set RZQ pin locations for the IP:
- Generate the IP or instantiate the IP into your project.
- You can view the available RZQ pins location in the Pin Planner. Go to Pin Planner > Tasks > OCT Pins and double click the RZQ. The available RZQ pins are display in the pin grid diagram.
- You can modify the qsf in your project to change the default RZQ location using the following command:
set_location_assignment <rzq_capable_pin_location> –to <user_defined_rzq_pin_name>
- Use the following command to associate the terminated pins of the IP with the RZQ pin:
set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_strobe_pin>
where * represents all the data pins within the same group.
set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_data_pin[*]>This is an example of a qsf file with modified RZQ pin location assignments:
set_location_assignment PIN_AH3 -to octrzq set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_strobe_io set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_data_io[*]
- Compile the project.
- To verify that the Intel® Quartus® Prime has successfully created and assigned the RZQ pin to the correct location, go to Pin Planner > Node Name and look for <user_defined_rzq_pin_name> with the assigned pin location in the list.
Did you find the information on this page useful?