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- 18.104.22.168.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers
4.2. Functional Description
The PHY Lite for Parallel Interfaces IP utilizes the I/O subsystem in the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, each column consists of I/O banks and I/O aux. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank.
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