E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 683702
Date 12/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives

For the latest and previous versions of this user guide, refer to E-Tile JESD204C Intel Agilex 7 FPGA IP Design Example User. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

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