E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

ID 683702
Date 12/21/2023

2.3. Generating the Design

To generate the design example from the IP parameter editor:

  1. Create a project targeting Intel Agilex® 7 E-Tile device family and select the desired device.
  2. In the IP Catalog, Tools > IP Catalog, select JESD204C Intel® FPGA IP .
  3. Specify a top-level name and the folder for your custom IP variation. Click OK.
  4. Select a design from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly. Alternatively, you can also specify your own settings and generate the design.
  5. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
  6. Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.