E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 683702
Date 12/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

3.1.2. Parallel I/O (PIO) Core

The parallel input/output (PIO) core with Avalon® interface provides a memory-mapped interface between an Avalon® memory-mapped slave port and general purpose I/O ports. The I/O ports connect either to on-chip user logic, or to I/O pins that connect to devices external to the FPGA.

Figure 7. PIO Core with Input Ports, Output Ports, and IRQ SupportBy default, the Platform Designer component disables the Interrupt Service Line (IRQ).

The PIO I/O ports are assigned at the top level HDL file (io_status for input ports, io_control for output ports).

The table below describes the signal connectivity for the status and control I/O ports to the DIP switch and LED on the development kit.

Table 9.  PIO Core I/O Ports
Port Bit Signal
Out_port 0 USER_LED SPI programming done
31:1 Reserved
In_port 0 USER_DIP internal serial loopback enable

Off = 1

On = 0
1 USER_DIP FPGA-generated SYSREF enable

Off = 1

On = 0
31:2 Reserved.
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