E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 683702
Date 12/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

2.5. Compiling and Testing the Design

The JESD204C Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  3. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Table 8.  Clock Settings
    Clock Name Clock Control GUI Clock Frequency
    refclk_xcvr Y2 (Si53311) Select the frequency for the transceiver PLL reference clock in the IP parameter editor.
    refclk_core Y2 (Si53311) Select the frequency for the core PLL reference clock in the IP parameter editor.
    mgmt_clk U36 (Si53311, CLK1) 100 MHz
    Figure 5. Clock Control GUI SettingThis example shows the clock control GUI setting for 24.333 Gbps data rate for the preset setting of LMF = 2812, 24.333 Gbps. Set the frequency according to the frequency you select for the PLL/CDR Reference Clock Frequency parameter in the IP parameter editor.
  4. If you are performing external loopback test, attach the QSFP-DD loopback module at cage (U12).
  5. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.
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