JESD204C Intel® Agilex™ FPGA IP Design Example User Guide

ID 683702
Date 11/22/2021
Public

2.3.2. Directory Structure

The JESD204C design example directories contain generated files for the design examples.
Figure 3. Directory Structure for JESD204C Intel® Agilex™ Design Example
Note: Intel® Agilex™ E-tile devices do not support Aldec Riviera-PRO* simulators.
Table 7.  Directory Files
Folders Files
ed/rtl
  • du
    • intel_j204c_ed_rx_tx.sv (top-level HDL file)
    • intel_j204c_ed_rx_tx.sdc
    • J204c_rx_tx_ip.qsys
    • j204c_rx_tx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
  • rx
    • intel_j204c_ed_rx.sv (top-level HDL file)
    • intel_j204c_ed_rx.sdc
    • j204c_rx_ip.qsys
    • j204c_rx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
  • tx
    • intel_j204c_ed_tx.sv (top-level HDL file)
    • intel_j204c_ed_tx.sdc
    • j204c_tx_ip.qsys
    • j204c_tx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
simulation/models
  • tb_top.sv
simulation/cadence
  • cadence_sim.sh
  • tb_top_wave.tcl
simulation/mentor
  • modelsim_sim.tcl
  • tb_top_waveform.do
simulation/synopsys
  • vcs
    • vcs_sim.sh
    • tb_top_wave_ed.do
  • vcsmx
    • vcsmx_sim.sh
    • tb_top_wave_ed.do
simulation/xcelium
  • xcelium_sim.sh
  • tb_top_wave.tcl
simulation/setup_scripts/common
  • modelsim_files.tcl
  • vcs_files.tcl
  • vcsmx_files.tcl
  • xcelium_files.tcl
simulation/setup_scripts/cadence
  • cds.lib
  • hdl.var
  • <cds_libs folder>
simulation/setup_scripts/mentor
  • msim_setup.tcl
simulation/setup_scripts/synopsys
  • vcs
    • vcs_setup.sh
  • vcsmx
    • vcsmx_setup.sh
    • synopsys_sim.setup
simulation/setup_scripts/xcelium
  • xcelium_setup.sh
  • cds.lib
  • hdl.var
  • <cds_libs folder>

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