E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

ID 683702
Date 12/21/2023

3. Detailed Description for the JESD204C Design Example

The JESD204C design example demonstrates the functionality of data streaming using loopback mode.

You can specify the parameters settings of your choice and generate the design example.

The design example is available only in duplex mode for both Base and PHY variant. You can choose Base only or PHY only variant but the IP would generate the design example for both Base and PHY.

Note: Some high data rate configurations may fail timing. To avoid timing failure, consider specifying lower frame clock frequency multiplier (FCLK_MULP) value in the Configurations tab of the JESD204C Intel® FPGA IP parameter editor.