E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 683702
Date 12/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.21 21.3 1.1.0
  • Text edits only; no new technical information.
  • Updated document title from JESD204C Intel® Agilex™ FPGA IP Design Example User Guide to E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide.
2023.02.10 21.3 1.1.0 Fixed the links in Table 1: Related Documents.
2021.11.22 21.3 1.1.0 Updated Compiling and Testing the Design to include related information about running the hardware testing using the Tcl script.
2021.11.01 21.3 1.1.0 Updated the JESD204C Intel Agilex® 7 FPGA IP Design Example Quick Start Guide chapter:
  • Added support for QuestaSim* simulator.
  • Removed references to the NCSim simulator.
2020.04.16 19.4 1.1.0
  • Added hardware support for the Intel Agilex® 7 design example.
  • Edited the following sections to include statement that says the design supports hardware testing:
    • JESD204C Intel Agilex® 7 FPGA IP Design Example Quick Start Guide
    • Generating the Design
  • Updated the Design Example Parameters to include information about the development kit.
  • Added the following new sections:
    • Compiling and Testing the Design
    • Hardware Test for System Console Control Design Example
  • Updated the description for the tst_ctl register in the JESD204C Design Example Control Registers section and the Test pattern parameter in the Design Example Parameters section. Starting Intel® Quartus® Prime Pro Edition software version 19.3 onwards, you can no longer use the [1:0] bit of the test control register to change the PRBS pattern. Use the Test pattern parameter instead.
2019.10.23 19.3 1.0.0 Initial release.
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