2.3.1. Design Example Parameters
||Select the system console control to access the design example data path through the system console.|
|Simulation||On, Off||Turn on for the IP to generate the necessary files for simulating the design example.|
|Synthesis||On, Off||Turn on for the IP to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.|
|HDL format (for simulation)||Verilog only||Select the HDL format of the RTL files for simulation.|
|HDL format (for synthesis)||Verilog only||Select the HDL format of the RTL files for synthesis.|
|Generate 3-wire SPI module||On, Off||
Turn on to enable 3-wire SPI interface instead of 4-wire.
Select whether you want the SYSREF alignment to be a one-shot pulse mode, periodic, or gapped periodic, based on your design requirements and timing flexibility.
||Select the board for the design example.
Select the patten generator and checker test pattern to either ramp or one of the PRBS pattern options.
The PRBS options are some of the commonly used degree of polynomials.
Note: To switch the PRBS polynomial options, change this parameter, and generate and recompile the design example.
If you select PRBS pattern, the pattern checker expects the scrambling seed to be self-synchronized when the deskew alignment is achieved by the JESD204C RX IP.
If you select ramp pattern, the first valid data sample for each converter (M) is loaded as the initial value. Subsequent data sample values must increase by 1 in each clock cycle up to the maximum and then roll over to 0. For example, when S=1, N=16 and WIDTH_MULP = 2, the data width per converter is S*WIDTH_MULP*N=32. The maximum data sample value is 0xFFFF.
The ramp pattern checker verifies that identical patterns are received across all converters.
|Enable internal serial loopback (Simulation)||On, Off||Turn on to enable internal serial loopback. If you turn on this option, the RX path takes the serial input from the TX path internally in the FPGA.|
|Enable command channel pattern (Simulation)||On, Off||Turn on to enable command channel pattern.|
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