E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

ID 683702
Date 12/21/2023

3.1. System Components

The JESD204C design example provides a software-based control flow that uses the hard control unit with or without system console support.

The design example enables an auto link up in internal and external loopback modes.

You can either configure your own settings or use one of the two presets provided.

  • L=2, M=8, F=12, with data rate of 24.333 Gbps
  • L=4, M=8, F=4, with data rate of 16.222 Gbps