E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

Download PDF
ID 683702
Date 12/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

2. JESD204C Intel® FPGA IP Design Example Quick Start Guide

The JESD204C Intel® FPGA IP design examples for Intel Agilex® 7 devices features a simulating testbench and a hardware design that supports compilation and hardware testing.

The JESD204C Intel® FPGA IP provides two preset settings for Intel Agilex® 7 E-Tile devices in duplex mode.

  • JESD204C design example for L=2, M=8, F=12, with data rate of 24.333 Gbps
  • JESD204C design example for L=4, M=8, F=4, with data rate of 16.222 Gbps

You can generate the JESD204C design examples through the IP catalog in the Intel® Quartus® Prime Pro Edition software.

Figure 1. Development Stages for the Design Example

Section Content
Design Example Block Diagram
Hardware and Software Requirements
Generating the Design
Compiling and Simulating the Design
Compiling and Testing the Design

Level Two Title