E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide

ID 683702
Date 12/21/2023

2. JESD204C Intel® FPGA IP Design Example Quick Start Guide

The JESD204C Intel® FPGA IP design examples for Intel Agilex® 7 devices features a simulating testbench and a hardware design that supports compilation and hardware testing.

The JESD204C Intel® FPGA IP provides two preset settings for Intel Agilex® 7 E-Tile devices in duplex mode.

  • JESD204C design example for L=2, M=8, F=12, with data rate of 24.333 Gbps
  • JESD204C design example for L=4, M=8, F=4, with data rate of 16.222 Gbps

You can generate the JESD204C design examples through the IP catalog in the Intel® Quartus® Prime Pro Edition software.

Figure 1. Development Stages for the Design Example