||Fixed the links in Table 1: Related Documents.
||Updated Compiling and Testing the Design to include related information about running the hardware testing using the Tcl script.
||Updated the JESD204C Intel® Agilex™ FPGA IP Design Example Quick Start Guide chapter:
- Added support for QuestaSim* simulator.
- Removed references to the NCSim simulator.
- Added hardware support for the Intel® Agilex™ design example.
- Edited the following sections to include statement that says the design supports hardware testing:
- JESD204C Intel® Agilex™ FPGA IP Design Example Quick Start Guide
- Generating the Design
- Updated the Design Example Parameters to include information about the development kit.
- Added the following new sections:
- Compiling and Testing the Design
- Hardware Test for System Console Control Design Example
- Updated the description for the tst_ctl register in the JESD204C Design Example Control Registers section and the Test pattern parameter in the Design Example Parameters section. Starting Intel® Quartus® Prime Pro Edition software version 19.3 onwards, you can no longer use the [1:0] bit of the test control register to change the PRBS pattern. Use the Test pattern parameter instead.