JESD204C Intel® Agilex™ FPGA IP Design Example User Guide

ID 683702
Date 2/10/2023
Public

5. Document Revision History for the JESD204C Intel® Agilex™ FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.02.10 21.3 1.1.0 Fixed the links in Table 1: Related Documents.
2021.11.22 21.3 1.1.0 Updated Compiling and Testing the Design to include related information about running the hardware testing using the Tcl script.
2021.11.01 21.3 1.1.0 Updated the JESD204C Intel® Agilex™ FPGA IP Design Example Quick Start Guide chapter:
  • Added support for QuestaSim* simulator.
  • Removed references to the NCSim simulator.
2020.04.16 19.4 1.1.0
  • Added hardware support for the Intel® Agilex™ design example.
  • Edited the following sections to include statement that says the design supports hardware testing:
    • JESD204C Intel® Agilex™ FPGA IP Design Example Quick Start Guide
    • Generating the Design
  • Updated the Design Example Parameters to include information about the development kit.
  • Added the following new sections:
    • Compiling and Testing the Design
    • Hardware Test for System Console Control Design Example
  • Updated the description for the tst_ctl register in the JESD204C Design Example Control Registers section and the Test pattern parameter in the Design Example Parameters section. Starting Intel® Quartus® Prime Pro Edition software version 19.3 onwards, you can no longer use the [1:0] bit of the test control register to change the PRBS pattern. Use the Test pattern parameter instead.
2019.10.23 19.3 1.0.0 Initial release.

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