eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Document Table of Contents

4.2.3. Supported Ethernet Variants

The eCPRI Intel FPGA IP pairs together with the 25G/10G Ethernet. The eCPRI IP is validated together with the 25G Ethernet for Stratix® 10 designs.

For your Stratix® 10 designs, you can select 25G Ethernet Intel FPGA IP for H-tile variants and E-tile Hard IP for Ethernet Intel FPGA IP for E-tile variants. When you use these IPs, you must set the following parameter values in the IP parameter editor:
  • Select Ethernet Rate if you use E-tile Hard IP for Ethernet Intel FPGA IP.
    Note: This option is not available with 25G Ethernet Intel FPGA IP. Use Enable 10G/25G dynamic rate switching for 10G data rate.
  • Enable Enable IEEE 1588 parameter to support client PTP message and eCPRI one-way delay measurement. The 25G Ethernet MAC only supports 96-bit (V2) timestamp format.
  • Disable Enable preamble pass-through and Enable TX CRC pass-through parameters.
  • Turn on Enable 10G/25G dynamic rate switching option to switch between 10G and 25G data rates.

For your Arria® 10 designs, you can use Low Latency Ethernet 10G MAC Intel FPGA IP and 1G/10GbE and 10GBASE-KR PHY Intel FPGA IP to implement MAC and PHY respectively for your Ethernet.