eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Public

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Document Table of Contents

4.1. Interfaces

The eCPRI Intel® FPGA IP supports several interfaces.

Clock and Reset Interface

The main interface for the clock and reset signals in the eCPRI IP.

Configuration Avalon® Memory-Mapped Interface

This interface provides access to the internal control and status registers of the eCPRI IP. This interface complies with Avalon® memory-mapped interface specification as defined in the Avalon® Interface Specifications.

External MAC Source Interface

This interface provides datapath from eCPRI IP to 25G Ethernet MAC IP. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

External MAC Sink Interface

This interface provides datapath from 25G Ethernet MAC IP to eCPRI IP. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

eCPRI IP Source Interface

This interface provides datapath from eCPRI IP to client logic. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

eCPRI IP Sink Interface

This interface provides datapath from client logic to eCPRI IP. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

IWF Type 0 eCPRI Source Interface

This interface provides datapath from eCPRI IP to IWF logic. This interface includes a number of sideband signals which align with the eCPRI IP source interface.

IWF Type 0 eCPRI Sink Interface

This interface provides datapath from IWF logic to eCPRI IP. This interface includes a number of sideband signals which align with the eCPRI IP source interface.

IWF Type 0 CPRI MAC Interface

This interface provides datapath from eCPRI IWF type 0 function to CPRI MAC. This interface consists of the following interfaces:

  • CPRI 32-bit IQ Data
  • CPRI 64-bit IQ Data
  • CPRI 32-bit Ctrl_AxC
  • CPRI 64-bit Ctrl_AxC
  • CPRI 32-bit Vendor Specific
  • CPRI 64-bit Vendor Specific
  • CPRI 32-bit Real-Time Vendor Specific
  • CPRI 64-bit Real-Time Vendor Specific
  • CPRI Gigabit Media Independent Interface (GMII)

External ST Source Interface

This interface provides datapath from eCPRI IP to client logic. This interface is a primary output interface for PTP and C&M messages. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock.

External ST Sink Interface

The IP has two external sink interfaces. These interfaces provide datapath from client logic to eCPRI IP. These interfaces are also primary inputs for PTP and C&M messages. These interfaces comply with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

TX and RX Time-of-Day (TOD) Interface

This interface provides 96-bit timestamp from PTP module to eCPRI IP core and to client logic.

Figure 6. eCPRI Intel® FPGA IP High-Level System Diagram