eCPRI Intel® FPGA IP User Guide

ID 683685
Date 5/18/2024
Public
Document Table of Contents

5.9. External ST Source Interface

Table 40.  Signals of the External ST Source InterfaceAll signals are synchronous to ext_sink_clk.
Signal Name Width (Bits) I/O Direction Description
ext_source_valid 1 Output Avalon® source valid from L2/L3 parser to external user logic.

This signal is synchronous to ext_sink_clk signal.

ext_source_data DATA_WIDTH 7 Output Avalon® source write data from L2/L3 parser to external user logic.
ext_source_sop 1 Output Avalon® source start of packet from L2/L3 parser to external user logic. Indicate the beginning of packet.
ext_source_eop 1 Output Avalon® source end of packet from L2/L3 parser to external user logic. Indicates the end of packet.
ext_source_empty LOG2(DATA_WIDTH7/8) Output Avalon® source empty from L2/L3 parser to external user logic. Indicates the number of symbols that are empty, that is, do not represent valid data.
ext_source_error 1 Output Avalon® source error from L2/L3 parser to external user logic. A bit mask to mark errors affecting the data being transferred in the current cycle.
ext_source_pkt_type 3 Output Indicate frame type of the packet output from L2/L3 parser to external user logic.
  • 000b: eCPRI
  • 001b: PTP
  • 010b: Misc

This signal is synchronous with ext_source_valid signal.

7 This is set to 64. This parameter is hidden from user and you can't change it.