eCPRI Intel® FPGA IP User Guide

ID 683685
Date 5/18/2024
Public
Document Table of Contents

5.7. Ethernet MAC Source Interface

Table 35.  Signals of the 25G Ethernet MAC Avalon® streaming interface Source Interface This section lists port from eCPRI IP to 25G Ethernet MAC. All signals are synchronous to mac_clk_tx.
Signal Name Width (Bits) I/O Direction Description
mac_source_valid 1 Output Indicates Avalon® source valid from eCPRI to Ethernet MAC.
mac_source_data DATA_WIDTH 3 Output Indicates Avalon® source write data from eCPRI to Ethernet MAC.
mac_source_sop 1 Output Indicates Avalon® source start of packet (SOP) from eCPRI to Ethernet MAC. Indicate the beginning of packet.
mac_source_eop 1 Output Avalon® source end of packet (EOP) from eCPRI to Ethernet MAC. Indicate the end of packet.
mac_source_empty LOG2(DATA_WIDTH3/8) Output Avalon® source empty from eCPRI to Ethernet MAC. Indicates the number of symbols that are empty, that is, do not represent valid data.
mac_source_ready 4 1 Input Avalon® source ready driven from Ethernet MAC. Indicate Ethernet MAC can accept data.
mac_source_error 1 Output Avalon® source error from eCPRI to Ethernet MAC. A bit mask to mark errors affecting the data being transferred in the current cycle.
3 This is set to 64. This parameter is hidden from user and you can't change it.
4 This signal has READY_LATENCY of 3 clock cycles.