eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Public
Document Table of Contents

5.15.10. CPRI IP L1 Control and Status Interface

Table 56.  Signals of CPRI IP L1 Control and Status Interface
Signal Name Width (Bits) I/O Direction Description
TX Interface
cpri_nego_bitrate_in[N] 6 Input CPRI line bit rate to be used in next attempt to achieve frame synchronization, encoded according to the following valid values:
  • 6'b000001: 0.6144 Gbps
  • 6'b000010: 1.2288 Gbps
  • 6'b000100: 2.4576 Gbps
  • 6'b000101: 3.0720 Gbps
  • 6'b001000: 4.9150 Gbps
  • 6'b001010: 6.1440 Gbps
  • 6'b010110: 8.11008 Gbps
  • 6'b010000: 9.8304 Gbps
  • 6'b010100: 10.1376 Gbps
  • 6b'011000: 12.16512 Gbps
  • 6'b110000 : 24.33024 Gbps
Note: IWF uses this information to determine the active interface (either 32-bit or 64-bit).
cpri_state_startup_seq[N] 6 Input Indicates the state of the CPRI start-up sequence state machine. This signal has the following valid values:
  • 3'b000: State A: Standby
  • 3'b001: State B: L1 Synchronization
  • 3'b011: State C: Protocol Setup
  • 3'b010: State D: Control and Management Setup
  • 3'b110: State E: Interface and VSS Negotiation
  • 3'b111: State F: Operation
  • 3'b101: State G: Passive Link
Note: Drive clk_csr with the same clock source as CPRI's reconfig_clk.
cpri_state_l1_synch[N] 3 Input
State B condition indicator. Indicates the state of the CPRI receiver L1 synchronization state machine. This signal has the following valid values:
  • 3'b000: XACQ1
  • 3'b001: XACQ2
  • 3'b011: XSYNC1
  • 3'b010: XSYNC2
  • 3'b110: HFNSYNC
cpri_local_lof[N] 1 Input The CPRI IP notifies the loss of frame detection to IWF block. In this case, the state_l1_synch signal indicates the L1 synchronization state machine is in state XACQ1 or XACQ2.
cpri_local_los[N] 1 Input The CPRI IP notifies the loss of frame detection to IWF block. The CPRI IP asserts this flag if it detects excessive 8B/10B or 64B/66B errors.
cpri_sdi_assert[N] 1 Output Indicates that the master service access point (SAP) is not available. Possible causes for this situation are equipment error or that the connected slave IP core is forwarding an SDI request it detected to the current RE CPRI master IP core through a direct connection.
cpri_local_rai[N] 1 Input Indicates that either the cpri_local_lof or the cpri_local_los signal is high; clears when both of those two signals are low. Logical OR of two output signals cpri_local_lof and cpri_local_los.
cpri_reset_assert[N] 1 Output Reset request from the application or from an RE slave to the current RE CPRI master IP core through a direct connection.
cpri_remote_lof[N] 1 Input Indicates LOF received in Z.130.0 control byte from remote CPRI link partner.

In this case the IP core also asserts the remote_lof bit in the FLSAR register at offset 0x2C.

cpri_remote_los[N] 1 Input Indicates LOS received in Z.130.0 control byte from remote CPRI link partner.

In this case the IP core also asserts the remote_los bit in the FLSAR register at offset 0x2C.

cpri_sdi_req[N] 1 Input Indicates remote SAP defect indication received in Z.130.0 control byte from remote CPRI link master. If the current CPRI IP core is an RE slave in a multi-hop configuration, you should connect this output signal directly to the cpri_sdi_assert input signal of the downstream RE master.
cpri_remote_rai[N] 1 Input Asserts when either cpri_remote_lof or cpri_remote_los is asserted, and clears when both cpri_remote_lof and z130_remote_los have the value of 0.

In this case the IP core also asserts the rai_detected bit in the FLSAR register at offset 0x2C.

cpri_reset_req[N]

1 Input If the current IP core is a CPRI link slave, indicates the IP core received a reset request in the Z.130.0 control byte from the remote CPRI link master.

If the current IP core is a CPRI link master, indicates the IP core received a reset acknowledgement in the Z.130.0 control byte from the remote CPRI link slave.