eCPRI Intel® FPGA IP User Guide

ID 683685
Date 5/18/2024
Public
Document Table of Contents

5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface

Table 53.  Signals of CPRI 32-bit Ctrl_AxC Interface
Signal Name Width (Bits) I/O Direction Description
TX Interface
rtvs32_tx_ready[N] 1 Input Indicates that CPRI mapper is ready to read a real-time vendor-specific byte from rtvs_tx_data on the next clock cycle.
rtvs32_tx_valid[N] 1 Output Write valid for rtvs_tx_data. Assert this signal to indicate rtvs_tx_data holds a valid value in the current clock cycle
rtvs32_tx_data[N] 64 Output Real-time vendor-specific word to be written to the CPRI frame.

The CPRI mapper writes the current value of the rtvs_tx_data bus to the CPRI frame based on the rtvs_tx_ready signal from the previous cycle, and the rtvs_tx_valid signal in the current cycle.

RX Interface
rtvs32_rx_valid[N] 1 Input Each asserted bit indicates the corresponding byte on the current rtvs_rx_data bus is a valid real-time vendor-specific byte.
rtvs32_rx_data[N] 64 Input Indicates real-time vendor-specific word received from the CPRI frame. The rtvs_rx_valid signal indicates which bytes are valid vendor specific bytes.