eCPRI Intel® FPGA IP User Guide

ID 683685
Date 5/18/2024
Public
Document Table of Contents

5.3. TX Time of Day Interface

Table 31.  Signals of the TX Time of Day InterfaceAll signals are synchronous to clk_tx clock.
Signal Name Width (Bits) I/O Direction Description
tx_tod_time_of_day_96b_data 96 Input Current V2-format (96-bit) TOD in clk_txmac clock domain.
tx_egress_timestamp_96b_data 96 Input

Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_96b_valid signal is asserted.

This signal is present only in two-step clock mode.

tx_egress_timestamp_96b_valid 1 Input Indicates that the tx_egress_timestamp_96b_data and tx_egress_timestamp_96b_fingerprint signals are valid in the current clk_txmac clock cycle.

This signal is present only in two-step clock mode.

tx_egress_timestamp_96b_fingerprint PTP_TS_FP_WIDTH + 2 Input Provides the fingerprint of the V2-format 1588 PTP frame currently beginning transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_96b_valid signal is asserted. Refer to section 4.2.1.
ext_tx_egress_timestamp_96b_data 96 Output Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link.

Value is valid when the tx_egress_timestamp_96b_valid signal is asserted.

ext_tx_egress_timestamp_96b_valid 1 Output Indicates that the ext_tx_egress_timestamp_96b_data signals are valid in the current ext_sink_clk clock cycle. This signal is meaningful only in two step clock mode.