eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Document Table of Contents

1.1. eCPRI Intel® FPGA IP Features

The IP offers the following features:
  • Compliant with the eCPRI Specification V2.0 (2018-06-25) available on the CPRI Industry Initiative (CII) website.
  • eCPRI radio equipment controller (eREC) and eCPRI radio equipment (eRE) module configurations.
  • Ethernet headers in a variety of formats, including VLAN tag, source/destination MAC address, IPv4, UDP extraction and encapsulation.
  • eCPRI one-way delay measurement based on IEEE Standard 1588 Precision Time Protocol (1588 PTP) hardware timestamp. Full hardware support, and required 1588 PTP software stack.
  • 25 Gbps and 10 Gbps Ethernet ports.
  • Pairing of eCPRI Intel FPGA IP with O-RAN Intel FPGA IP.
  • Interworking function (IWF) type 0 between eCPRI node and one CPRI node.
  • Can Ethernet streaming frame size up to 9,000 bytes as defined by Ethernet jumbo frames standard.
  • Packet classifier to classify eCPRI packet and send packets to eCPRI IP. The IP redirects all other packets to external port for user processing.
  • Programmable packet queue (maximum 16 entries) holds incoming packets when eCPRI packets transmission in progress.
  • Arbitration between eCPRI packet and external incoming Ethernet frames, e.g., Control & Management (C&M) and synchronization packets.
  • Mapping logic between eCPRI message physical channel ID to VLAN/MAC address CSR.
  • Single distributed unit (DU) and up to eight radio unit (RU) configurations using source/destination MAC address CSR.
  • All eCPRI message types compliant to eCPRI specification v2.0
  • Input and output ports compliant with Avalon® streaming interface .
Table 1.   eCPRI Intel® FPGA IP Feature Matrix
Device Support Data Rate
Agilex™ 5 10G
Agilex™ 7 25G
Agilex™ 9 10G
Stratix® 10 25G
Arria® 10 10G