eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Document Table of Contents

6. eCPRI IP Registers

The IP registers are 32-bits wide and are accessible using the Avalon® memory-mapped interface. This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 57.  Register Access Codes
Code Description
RW Read and write
RO Read only
RW1C Read, write, and clear. Your application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) on executing instructions.